About Junhao Ye
Hi! I am Junhao Ye (叶俊豪), a Ph.D. candidate in the School of Integrated Circuits at Southeast University, advised by Prof. Zhe Jiang. I received my B.S. in Microelectronics Science and Engineering from Shenzhen University, ranking 1/103 in the comprehensive evaluation.
My research focuses on AI for Electronic Design Automation (EDA), especially LLM-aided RTL verification. I study UVM-based automation spanning testbench and stimulus generation, simulation feedback and refinement; assertion generation; and SoC security detection.
I have published 4 papers at the leading EDA conferences ICCAD and DAC. I am also a research intern at the National Center for Technology Innovation in EDA, where some of my research work has been integrated into ChatDV to support end-to-end automated UVM verification for small IPs. I have received the National Scholarship, Excellent Star of SZU, and Jicui Graduate honors.
你好!我是叶俊豪,东南大学集成电路学院博士生,师从江哲教授。本科毕业于深圳大学,专业排名 1/103。我的研究聚焦 AI for EDA,重点关注以 UVM 为核心的自动化验证闭环。